A) Field of the Invention
The present invention relates to a polysilicon etching method suitable for use in manufacturing a semiconductor device such as a semiconductor memory having a multilayer gate electrode structure or a stacked capacitor electrode structure.
B) Description of the Related Art
Electrically erasable and programmable read only memories (EEPROM) and flash memories are known as semiconductor memories having a multilayer gate electrode structure. Dynamic random access memories (DRAM) are known as semiconductor memories having a stacked capacitor electrode structure. During the manufacture of these memories, it is required to precisely etch and pattern a polysilicon layer which is deposited covering a protrusion having a vertical side wall of about 0.3 μm.
In a conventional polysilicon etching method satisfying such requirements, a high density plasma etching process is divided into first and second steps. At the first step, a polysilicon layer is selectively etched by using mixture gas of HBr, Cl2 and O2 at a low pressure of 2 to 8 mTorr. At the second step, polysilicon residues are etched by using mixture gas of HBr and O2 at a high pressure of 20 to 40 mTorr. (This method is called a first conventional method. For example, refer to Patent Gazette No. 2,822,952.)
In another conventional polysilicon etching method, a polysilicon layer is selectively etched by reactive ion etching (RIE) by using mixture gas of HBr, Ar and O2. (This method is called a second conventional method. For example, refer to Patent Gazette No. 3,088,178.)
In still another conventional polysilicon etching method, at a first anisotropic etching step, a polysilicon layer is selectively etched by using mixture gas of CCl4 and He, and at a second anisotropic etching step, etching residues are removed by utilizing plasma scattering phenomenon by using mixture gas of CCl4, He and SF6. (This method is called a third conventional method. For example, refer to Patent Gazette No. 2,574,045.)
According to the third conventional method, since isotropic etching progresses by the plasma scattering phenomenon, an abnormal shape called notching is formed at the interface between the polysilicon layer and an underlying film. According to the second conventional method, since Ar ions suppress the formation of a deposition film on the side walls of the polysilicon layer, the polysilicon layer is likely to be subjected to side etching (undercut), resulting in a lowered size precision.
The first conventional method can solve the problems of the second and third conventional methods. However, if a space between adjacent resist layers becomes as narrow as about 0.4 μm, polysilicon residues left on the side walls of a protrusion having a height of 0.3 μm cannot be removed completely by over-etch using mixture gas of HBr and O2.